-- By : Itf2Vhdl ver. 1.20

--

-- Description : курсовой проект по МИУС Куприенко Алексея--

-- Description :

-- Design unit header --

library IEEE;

use IEEE.std_logic_1164.all;

entity BME is

port(

K1R1 : in STD_LOGIC;

K1R2 : in STD_LOGIC;

K2R1 : in STD_LOGIC;

K2R2 : in STD_LOGIC;

K3R1 : in STD_LOGIC;

K3R2 : in STD_LOGIC;

SSVR11 : out STD_LOGIC;

SSVR12 : out STD_LOGIC;

SSVR21 : out STD_LOGIC;

SSVR22 : out STD_LOGIC;

SSVR31 : out STD_LOGIC;

SSVR32 : out STD_LOGIC

);

end BME;

architecture BME of BME is

---- Component declarations -----

component FE

port (

In1 : in STD_LOGIC;

In2 : in STD_LOGIC;

Out1 : out STD_LOGIC;

Out2 : out STD_LOGIC

);

end component;

component spt

port (

In1 : in STD_LOGIC;

In2 : in STD_LOGIC;

In3 : in STD_LOGIC;

In4 : in STD_LOGIC;

Out1 : out STD_LOGIC;

Out2 : out STD_LOGIC

);

end component;

---- Signal declarations used on the diagram ----

signal NET122 : STD_LOGIC;

signal NET126 : STD_LOGIC;

signal NET130 : STD_LOGIC;

signal NET134 : STD_LOGIC;

signal NET138 : STD_LOGIC;

signal NET142 : STD_LOGIC;

signal NET295 : STD_LOGIC;

signal NET299 : STD_LOGIC;

signal NET303 : STD_LOGIC;

signal NET307 : STD_LOGIC;

signal NET317 : STD_LOGIC;

signal NET321 : STD_LOGIC;

begin

---- Component instantiations ----

U1 : spt

port map(

In1 => K2R1,

In2 => K2R2,

In3 => NET138,

In4 => NET142,

Out1 => NET303,

Out2 => NET307

);

U10 : FE

port map(

In1 => NET303,

In2 => NET307,

Out1 => SSVR21,

Out2 => SSVR22

);

U11 : FE

port map(

In1 => NET295,

In2 => NET299,

Out1 => SSVR11,

Out2 => SSVR12

);

U12 : FE

port map(

In1 => NET317,

In2 => NET321,

Out1 => SSVR31,

Out2 => SSVR32

);

U2 : spt

port map(

In1 => K1R1,

In2 => K1R2,

In3 => NET122,

In4 => NET126,

Out1 => NET295,

Out2 => NET299

);

U3 : spt

port map(

In1 => K3R1,

In2 => K3R2,

In3 => NET130,

In4 => NET134,

Out1 => NET317,

Out2 => NET321

);

NET142 <= not(K3R2);

NET138 <= not(K3R1);

NET126 <= not(K2R2);

NET122 <= not(K2R1);

NET134 <= not(K1R2);

NET130 <= not(K1R1);

end BME;

-- Title : Фиксирующий элемент

-- Design : First

-- Author : 123

-- Company : 456

--

-- Description :

--

-- Design unit header --

library IEEE;

use IEEE.std_logic_1164.all;

-- other libraries declarations

-- synopsys translate_off

library VIRTEX;

library IEEE;

use IEEE.vital_timing.all;

-- synopsys translate_on

entity FE is

port(

In1 : in STD_LOGIC;

In2 : in STD_LOGIC;

Out1 : out STD_LOGIC;

Out2 : out STD_LOGIC

);

end FE;

architecture FE of FE is

---- Component declarations -----

component pt

port (

Reset : in STD_LOGIC;

Set : in STD_LOGIC;

T0 : in STD_LOGIC;

T1 : in STD_LOGIC;

Q0 : out STD_LOGIC;

nQ0 : out STD_LOGIC

);

end component;

component ptgen

port (

Y : out STD_LOGIC;

nY : out STD_LOGIC

);

end component;

component sbros

port (

Y : out STD_LOGIC

);

end component;

component spt

port (

In1 : in STD_LOGIC;

In2 : in STD_LOGIC;

In3 : in STD_LOGIC;

In4 : in STD_LOGIC;

Out1 : out STD_LOGIC;

Out2 : out STD_LOGIC

);

end component;

component Vosstan

port (

Y : out STD_LOGIC

);

end component;

component VCC

-- synopsys translate_off

generic(

InstancePath : STRING := "*";

MsgOn : BOOLEAN := False;

TimingChecksOn : BOOLEAN := false;

Xon : BOOLEAN := TRUE

);

-- synopsys translate_on

port (

P : out std_ulogic := '1'

);

end component;

---- Signal declarations used on the diagram ----

signal NET101 : STD_LOGIC;

signal NET260 : STD_LOGIC;

signal NET264 : STD_LOGIC;

signal NET276 : STD_LOGIC;

signal NET308 : STD_LOGIC;

signal NET387 : STD_LOGIC;

signal NET394 : STD_LOGIC;

signal NET398 : STD_LOGIC;

signal NET404 : STD_LOGIC;

signal NET414 : STD_LOGIC;

signal NET418 : STD_LOGIC;

signal NET422 : STD_LOGIC;

signal NET453 : STD_LOGIC;

signal NET458 : STD_LOGIC;

signal NET572 : STD_LOGIC;

signal NET576 : STD_LOGIC;

signal NET639 : STD_LOGIC;

signal NET707 : STD_LOGIC;

signal NET716 : STD_LOGIC;

signal NET97 : STD_LOGIC;

---- Configuration specifications for declared components

-- synopsys translate_off

for U6 : VCC use entity VIRTEX.VCC;

-- synopsys translate_on

-- synopsys translate_off

for U7 : VCC use entity VIRTEX.VCC;

-- synopsys translate_on

begin

---- Component instantiations ----

U1 : spt

port map(

In1 => In1,

In2 => NET97,

In3 => NET101,

In4 => In2,

Out1 => NET260,

Out2 => NET264

);

NET422 <= not(NET639);

NET418 <= not(NET422);

NET414 <= not(NET418);

NET453 <= NET639 and NET414;

NET458 <= not(NET453);

NET576 <= NET572 and NET458;

Out1 <= NET716;

Out2 <= NET707;

U18 : sbros

port map(

Y => NET572

);

U2 : ptgen

port map(

Y => NET97,

nY => NET101

);

U3 : Vosstan

port map(

Y => NET387

);

U4 : pt

port map(

Q0 => NET394,

Reset => NET308,

Set => NET387,

T0 => NET707,

T1 => NET716,

nQ0 => NET398

);

U5 : pt

port map(

Q0 => NET716,

Reset => NET576,

Set => NET276,

T0 => NET264,

T1 => NET260,

nQ0 => NET707

);

U6 : VCC

port map(

P => NET308

);

U7 : VCC

port map(

P => NET276

);

NET639 <= not(NET404);

NET404 <= NET398 xor NET394;

end FE;

--------------------------------------------------------------------------------------------

-- Title : 2-4 СПТ

-- Design : First

-- Author : 123

-- Company : 456

-- Description :

-- Design unit header --

library IEEE;

use IEEE.std_logic_1164.all;

entity spt is

port(

In1 : in STD_LOGIC;

In2 : in STD_LOGIC;

In3 : in STD_LOGIC;

In4 : in STD_LOGIC;

Out1 : out STD_LOGIC;

Out2 : out STD_LOGIC

);

end spt;

architecture spt of spt is

---- Signal declarations used on the diagram ----

signal NET107 : STD_LOGIC;

signal NET115 : STD_LOGIC;

signal NET91 : STD_LOGIC;

signal NET99 : STD_LOGIC;

begin

---- Component instantiations ----

NET91 <= In2 or In1;

NET99 <= In4 or In3;

NET107 <= In2 and In1;

NET115 <= In4 and In3;

Out1 <= NET99 and NET91;

Out2 <= NET115 or NET107;

end spt;

--------------------------------------------------------------------------------------------

-- Title : Парафазный триггер

-- Design : First

-- Author : 123

-- Company : 456

--

-- Description :

-- Design unit header --

library IEEE;

use IEEE.std_logic_1164.all;

entity pt is

port(

Reset : in STD_LOGIC;

Set : in STD_LOGIC;

T0 : in STD_LOGIC;

T1 : in STD_LOGIC;

Q0 : out STD_LOGIC;

nQ0 : out STD_LOGIC

);

end pt;

architecture pt of pt is

---- Signal declarations used on the diagram ----

signal NET102 : STD_LOGIC;

signal NET204 : STD_LOGIC;

signal NET230 : STD_LOGIC;

signal NET232 : STD_LOGIC;

signal NET236 : STD_LOGIC;

signal NET239 : STD_LOGIC;

signal NET240 : STD_LOGIC;

signal NET340 : STD_LOGIC;

signal NET343 : STD_LOGIC;

signal NET344 : STD_LOGIC;

signal NET444 : STD_LOGIC;

signal NET447 : STD_LOGIC;

signal NET448 : STD_LOGIC;

signal NET556 : STD_LOGIC;

signal NET568 : STD_LOGIC;

signal NET580 : STD_LOGIC;

signal NET592 : STD_LOGIC;

signal NET67 : STD_LOGIC;

signal NET71 : STD_LOGIC;

signal NET88 : STD_LOGIC;

begin

---- Component instantiations ----

NET204 <= not(NET102 and Reset and T0);

NET239 <= not(NET236);

NET230 <= not(NET240);

NET568 <= not(NET239);

NET232 <= not(NET230);

nQ0 <= NET232 or NET240;

NET340 <= not(NET344 and Set and T1);

NET344 <= not(NET568 and Reset and NET340);

NET343 <= not(NET340);

NET556 <= not(NET343);

NET102 <= not(NET556 and Set and NET204);

NET444 <= not(NET448 and Reset and T1);

NET448 <= not(NET592 and Set and NET444);

NET447 <= not(NET444);

NET580 <= not(NET447);

NET88 <= not(NET204);

NET67 <= not(NET102);

NET592 <= not(NET88);

NET71 <= not(NET67);

Q0 <= NET71 or NET102;

NET236 <= not(NET240 and Set and T0);

NET240 <= not(NET580 and Reset and NET236);

end pt;

-- Title : Парафазный генератор

-- Design : First

-- Author : 123

-- Company : 456

-- Description :

-- Design unit header --

library IEEE;

use IEEE.std_logic_1164.all;

Entity PTGen is

Port (

Y : out STD_LOGIC;

nY : out STD_LOGIC);

End PTGen;

Architecture STRUCTURA of PTGen is

constant CLK_PERIOD: TIME := 10 us;

begin

CLK_GEN: process

begin

Y <= '0';

nY <= '1';

wait for CLK_PERIOD/2;

Y <= '1';

nY <= '0';

wait for CLK_PERIOD/2;

end process;

end STRUCTURA;

--------------------------------------------------------------------------------------------

-- Title : Формирователь сигнала восстановления ПТ2

-- Design : First

-- Author : 123

-- Company : 456

-- Description :

-- Design unit header --

library IEEE;

use IEEE.std_logic_1164.all;

Entity Vosstan is

Port (

Y : out STD_LOGIC);

End Vosstan;

Architecture STRUCTURA of PTGen is

begin

CLK_GEN: process

variable i:bit:='0';

begin

if i='0' then

wait for 7us;

i:='1';

end if;

Y <= '1';

wait for 0.3us;

Y <= '0';

wait for 82us;

end process;

end STRUCTURA;

--------------------------------------------------------------------------------------------

-- Title : Формирователь сигнала начального сброса ПТ1

-- Design : First

-- Author : 123

-- Company : 456

-- Description :

-- Design unit header --

library IEEE;

use IEEE.std_logic_1164.all;

Entity sbros is

Port (

Y : out STD_LOGIC );

End sbros;

Architecture STRUCTURA of sbros is

begin

process

begin

Y <= '1';

wait for 6 us;

Y <= '0';

end process;

end STRUCTURA;

Размещено на Allbest.ru