SIGNAL Sum_Im: SIGNED(X_Y_WIDTH + W_SIZE_CD+1+8 downto 0);

begin

process (CLK_160)

begin

IF RISING_EDGE (CLK_160)THEN

MS_160 <= MS;

MS_160D <= MS_160;

MS_M160 <= (NOT MS_160D) AND MS_160;

END IF;

end process;

process (CLK_160) -- corellation Enable

begin

IF RISING_EDGE (CLK_160)THEN

IF NRD = '1' AND MS(1) = '1' THEN

CORR_ENA <= '1';

ELSIF

(KRDNS = '1' AND MS(1) = '1')

THEN

CORR_ENA <= '0';

ELSE CORR_ENA <= CORR_ENA;

END IF;

END IF;

end process;

process (CLK_160) -- multip Enable

begin

IF RISING_EDGE (CLK_160)THEN

IF MS_M160(1) = '1' and CORR_ENA = '1' THEN

mult_ENA <= '1';

ELSIF (COUNT_H1 = (corr_depth/4)-2 and CORR_ENA = '1') THEN

mult_ENA <= '0';

ELSE mult_ENA <= mult_ENA;

END IF;

END IF;

end process;

--

process (clk_160) --shifting and sorting X/Y

begin

if (rising_edge(clk_160)) then

if (COUNT_H1P = 0 and MS_M160(1) = '1') then

is lost

X_SH((corr_depth-1) downto 1) <= X_SH((corr_depth-2) downto 0);

Y_SH((corr_depth-1) downto 1) <= Y_SH((corr_depth-2) downto 0);

-- Load new data into the first stage

X_SH(0) <= in_X;

Y_SH(0) <= in_Y;

end if;

case (en_o) is

when '1' =>

out_X1I (X_Y_WIDTH-1 downto 0) <= X_SH(COUNT_H1);

out_X2I (X_Y_WIDTH-1 downto 0) <= X_SH(COUNT_H2);

out_X3I (X_Y_WIDTH-1 downto 0) <= X_SH(COUNT_H3);

out_X4I (X_Y_WIDTH-1 downto 0) <= X_SH(COUNT_H4);

out_Y1I (X_Y_WIDTH-1 downto 0)<= Y_SH(COUNT_H1);

out_Y2I (X_Y_WIDTH-1 downto 0)<= Y_SH(COUNT_H2);

out_Y3I (X_Y_WIDTH-1 downto 0)<= Y_SH(COUNT_H3);

out_Y4I (X_Y_WIDTH-1 downto 0)<= Y_SH(COUNT_H4);

out_X1I (X_Y_WIDTH)<= X_SH(COUNT_H1)(X_Y_WIDTH-1);

out_X2I (X_Y_WIDTH)<= X_SH(COUNT_H2)(X_Y_WIDTH-1);

out_X3I (X_Y_WIDTH)<= X_SH(COUNT_H3)(X_Y_WIDTH-1);

out_X4I (X_Y_WIDTH)<= X_SH(COUNT_H4)(X_Y_WIDTH-1);

out_Y1I (X_Y_WIDTH)<= Y_SH(COUNT_H1)(X_Y_WIDTH-1);

out_Y2I (X_Y_WIDTH)<= Y_SH(COUNT_H2)(X_Y_WIDTH-1);

out_Y3I (X_Y_WIDTH)<= Y_SH(COUNT_H3)(X_Y_WIDTH-1);

out_Y4I (X_Y_WIDTH)<= Y_SH(COUNT_H4)(X_Y_WIDTH-1);

when others =>

out_X1I (X_Y_WIDTH downto 0) <= "00000000000000";

out_X2I (X_Y_WIDTH downto 0) <= "00000000000000";

out_X3I (X_Y_WIDTH downto 0) <= "00000000000000";

out_X4I (X_Y_WIDTH downto 0) <= "00000000000000";

out_Y1I (X_Y_WIDTH downto 0)<= "00000000000000";

out_Y2I (X_Y_WIDTH downto 0)<= "00000000000000";

out_Y3I (X_Y_WIDTH downto 0)<= "00000000000000";

out_Y4I (X_Y_WIDTH downto 0)<= "00000000000000";

end case;

end if;

end process;

--------------------

C1<=CD1 (W_SIZE_CD downto 0);

D1<=CD1 (2*W_SIZE_CD+1 downto W_SIZE_CD+1);

C2<=CD2 (W_SIZE_CD downto 0);

D2<=CD2 (2*W_SIZE_CD+1 downto W_SIZE_CD+1);

C3<=CD3 (W_SIZE_CD downto 0);

D3<=CD3 (2*W_SIZE_CD+1 downto W_SIZE_CD+1);

C4<=CD4 (W_SIZE_CD downto 0);

D4<=CD4 (2*W_SIZE_CD+1 downto W_SIZE_CD+1);

--------------------

addr_CD <= COUNT_H1;

out_X <= XI_1;

out_C <= DI_1;

out_CC <= DI_2;

out_CCC <= DI_3;

out_CCCC <= DI_4;

corr <= corr_ena;

process (clk_160) --complex multiplyer

begin

IF RISING_EDGE (clk_160) THEN

XI_1<=out_X1I; YI_1<=out_Y1I;

CI_1<=C1; DI_1<=D1;

XI1_1<=XI_1;

CI1_1<=CI_1; DI1_1<=DI_1;

XI_2<=out_X2I; YI_2<=out_Y2I;

CI_2<=C2; DI_2<=D2;

XI1_2<=XI_2;

CI1_2<=CI_2; DI1_2<=DI_2;

XI_3<=out_X3I; YI_3<=out_Y3I;

CI_3<=C3; DI_3<=D3;

XI1_3<=XI_3;

CI1_3<=CI_3; DI1_3<=DI_3;

XI_4<=out_X4I; YI_4<=out_Y4I;

CI_4<=C4; DI_4<=D4;

XI1_4<=XI_4;

CI1_4<=CI_4; DI1_4<=DI_4;

END IF;

IF RISING_EDGE (clk_160) THEN

CpD_1<=CI_1 + DI_1;

XpY_1<=XI_1 + YI_1;

YmX_1<=YI_1 - XI_1;

CpD_2<=CI_2 + DI_2;

XpY_2<=XI_2 + YI_2;

YmX_2<=YI_2 - XI_2;

CpD_3<=CI_3 + DI_3;

XpY_3<=XI_3 + YI_3;

YmX_3<=YI_3 - XI_3;

CpD_4<=CI_4 + DI_4;

XpY_4<=XI_4 + YI_4;

YmX_4<=YI_4 - XI_4;

END IF;

IF RISING_EDGE (clk_160) THEN

--

K2_1<=XpY_1*DI1_1;

K1_1<=CpD_1*XI1_1;

K3_1<=YmX_1*CI1_1;

--

K2_2<=XpY_2*DI1_2;

K1_2<=CpD_2*XI1_2;

K3_2<=YmX_2*CI1_2;

--

K2_3<=XpY_3*DI1_3;

K1_3<=CpD_3*XI1_3;

K3_3<=YmX_3*CI1_3;

--

K2_4<=XpY_4*DI1_4;

K1_4<=CpD_4*XI1_4;

K3_4<=YmX_4*CI1_4;

END IF;

--

IF RISING_EDGE (clk_160) THEN

Re1<=K1_1-K2_1;

Im1<=K1_1+K3_1;

Re2<=K1_2-K2_2;

Im2<=K1_2+K3_2;

Re3<=K1_3-K2_3;

Im3<=K1_3+K3_3;

Re4<=K1_4-K2_4;

Im4<=K1_4+K3_4;

END IF;

end process;

process (clk_160)

begin

-- IF RISING_EDGE (clk_160) THEN

IF (timer=0) THEN --ACCUMULATOR

-- Clear the accumulated data

accRe1 <= "00000000000000000000000000";

accIm1 <= "00000000000000000000000000";

accRe2 <= "00000000000000000000000000";

accIm2 <= "00000000000000000000000000";

accRe3 <= "00000000000000000000000000";

accIm3 <= "00000000000000000000000000";

accRe4 <= "00000000000000000000000000";

accIm4 <= "00000000000000000000000000";

ELSE

accRe1 <= addRe1_out;

accIm1 <= addIm1_out;

accRe2 <= addRe2_out;

accIm2 <= addIm2_out;

accRe3 <= addRe3_out;

accIm3 <= addIm3_out;

accRe4 <= addRe4_out;

accIm4 <= addIm4_out;

END IF;

-- END IF;

IF RISING_EDGE (clk_160) THEN -- Store accumulation result in a register

IF timer=0 THEN --сброс регистра аккумулятора по timer

addRe1_out <= "00000000000000000000000000";

addIm1_out <= "00000000000000000000000000";

addRe2_out <= "00000000000000000000000000";

addIm2_out <= "00000000000000000000000000";

addRe3_out <= "00000000000000000000000000";

addIm3_out <= "00000000000000000000000000";

addRe4_out <= "00000000000000000000000000";

addIm4_out <= "00000000000000000000000000";

ELSE

IF timer > 5 and timer < 71 THEN

addRe1_out <= (Re1 + accRe1);

addIm1_out <= (Im1 + accIm1);

addRe2_out <= (Re2 + accRe2);

addIm2_out <= (Im2 + accIm2);

addRe3_out <= (Re3 + accRe3);

addIm3_out <= (Im3 + accIm3);

addRe4_out <= (Re4 + accRe4);

addIm4_out <= (Im4 + accIm4);

END IF;

END IF;

END IF;

IF RISING_EDGE (clk_160) THEN --accum result --(X_Y_WIDTH + W_SIZE_CD+1+7 downto 0)

IF timer=72 THEN

Acc_Re_1(X_Y_WIDTH + W_SIZE_CD+1+6 downto 0)<=addRe1_out;

Acc_Im_1(X_Y_WIDTH + W_SIZE_CD+1+6 downto 0)<=addIm1_out;

Acc_Re_2(X_Y_WIDTH + W_SIZE_CD+1+6 downto 0)<=addRe2_out;

Acc_Im_2(X_Y_WIDTH + W_SIZE_CD+1+6 downto 0)<=addIm2_out;

Acc_Re_3(X_Y_WIDTH + W_SIZE_CD+1+6 downto 0)<=addRe3_out;

Acc_Im_3(X_Y_WIDTH + W_SIZE_CD+1+6 downto 0)<=addIm3_out;

Acc_Re_4(X_Y_WIDTH + W_SIZE_CD+1+6 downto 0)<=addRe4_out;

Acc_Im_4(X_Y_WIDTH + W_SIZE_CD+1+6 downto 0)<=addIm4_out;

--

Acc_Re_1(X_Y_WIDTH + W_SIZE_CD+1+7)<=addRe1_out(X_Y_WIDTH + W_SIZE_CD+1+6);

Acc_Im_1(X_Y_WIDTH + W_SIZE_CD+1+7)<=addIm1_out(X_Y_WIDTH + W_SIZE_CD+1+6);

Acc_Re_2(X_Y_WIDTH + W_SIZE_CD+1+7)<=addRe2_out(X_Y_WIDTH + W_SIZE_CD+1+6);

Acc_Im_2(X_Y_WIDTH + W_SIZE_CD+1+7)<=addIm2_out(X_Y_WIDTH + W_SIZE_CD+1+6);

Acc_Re_3(X_Y_WIDTH + W_SIZE_CD+1+7)<=addRe3_out(X_Y_WIDTH + W_SIZE_CD+1+6);

Acc_Im_3(X_Y_WIDTH + W_SIZE_CD+1+7)<=addIm3_out(X_Y_WIDTH + W_SIZE_CD+1+6);

Acc_Re_4(X_Y_WIDTH + W_SIZE_CD+1+7)<=addRe4_out(X_Y_WIDTH + W_SIZE_CD+1+6);

Acc_Im_4(X_Y_WIDTH + W_SIZE_CD+1+7)<=addIm4_out(X_Y_WIDTH + W_SIZE_CD+1+6);

--

Acc_Re_1(X_Y_WIDTH + W_SIZE_CD+1+8)<=addRe1_out(X_Y_WIDTH + W_SIZE_CD+1+6);

Acc_Im_1(X_Y_WIDTH + W_SIZE_CD+1+8)<=addIm1_out(X_Y_WIDTH + W_SIZE_CD+1+6);

Acc_Re_2(X_Y_WIDTH + W_SIZE_CD+1+8)<=addRe2_out(X_Y_WIDTH + W_SIZE_CD+1+6);

Acc_Im_2(X_Y_WIDTH + W_SIZE_CD+1+8)<=addIm2_out(X_Y_WIDTH + W_SIZE_CD+1+6);

Acc_Re_3(X_Y_WIDTH + W_SIZE_CD+1+8)<=addRe3_out(X_Y_WIDTH + W_SIZE_CD+1+6);

Acc_Im_3(X_Y_WIDTH + W_SIZE_CD+1+8)<=addIm3_out(X_Y_WIDTH + W_SIZE_CD+1+6);

Acc_Re_4(X_Y_WIDTH + W_SIZE_CD+1+8)<=addRe4_out(X_Y_WIDTH + W_SIZE_CD+1+6);

Acc_Im_4(X_Y_WIDTH + W_SIZE_CD+1+8)<=addIm4_out(X_Y_WIDTH + W_SIZE_CD+1+6);

END IF;

END IF;

IF RISING_EDGE (clk_160) THEN --accum summ

Sum_Re_1_2<=Acc_Re_1+Acc_Re_2;

Sum_Im_1_2<=Acc_Im_1+Acc_Im_2;

Sum_Re_3_4<=Acc_Re_3+Acc_Re_4;

Sum_Im_3_4<=Acc_Im_3+Acc_Im_4;

END IF;

IF RISING_EDGE (clk_160) THEN --accum summ

Sum_Re<=Sum_Re_1_2+Sum_Re_3_4;

Sum_Im<=Sum_Im_1_2+Sum_Im_3_4;

END IF;

END PROCESS;

out_XR<=Sum_Re;

out_YR<=Sum_Im;

out_X1<=Acc_Re_1;

out_Y1<=Acc_Im_1;

out_X2<=Acc_Re_2;

out_Y2<=Acc_Im_2;

out_X3<=Acc_Re_3;

out_Y3<=Acc_Im_3;

out_X4<=Acc_Re_4;

out_Y4<=Acc_Im_4;

process (clk_160) --shift C_D

begin

null;

end process;

process (CLK_160) -- counter Z

begin

IF RISING_EDGE (CLK_160)THEN

IF RES_160 = '1' THEN

COUNT_Z <= 0;

ELSIF (COUNT_H1 = 1) THEN

COUNT_Z <= COUNT_Z + 1;

ELSE

COUNT_Z <= COUNT_Z;

END IF;

END IF;

end process;

process (CLK_160) -- counter h

begin

IF RISING_EDGE (CLK_160)THEN

RES_160 <= NRD AND MS(1) AND not CORR_ENA;

RES_160D <= RES_160;

RES_M160 <= (NOT RES_160D) AND RES_160;

END IF;

COUNT_H <= COUNT_H1P;

IF RISING_EDGE (CLK_160)THEN

COUNT_H4 <= COUNT_H + ((3*corr_depth)/4);

COUNT_H3 <= COUNT_H + ((2*corr_depth)/4);

COUNT_H2 <= COUNT_H + (corr_depth/4);

COUNT_H1 <= COUNT_H + 0;

IF RES_160 = '1' THEN

COUNT_H1P <= 0;

ELSIF (CORR_ENA = '1' and mult_ENA = '1') THEN

COUNT_H1P <= COUNT_H1P + 1;

END IF;

END IF;

IF RISING_EDGE (CLK_160)THEN

IF MS_M160(1) = '1' THEN

timer <= 0;

ELSIF (CORR_ENA = '1') THEN

timer <= timer + 1;

END IF;

END IF;

end process;

process (CLK_160) -- out enabling

begin

IF RISING_EDGE (CLK_160)THEN

IF timer = 0 THEN

en_o <= '1';

ELSIF timer = (corr_depth/4) THEN

en_o <= '0';

ELSE en_o <= en_o;

END IF;

END IF;

end process;

out_en <= en_o;

end Behavioral;

Приложение Б - программный код модуля «mem_drv»

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

use IEEE.STD_LOGIC_SIGNED.ALL;

entity mem_drv is

generic

(corr_depth : natural := 256;

W_SIZE_CD : natural := 6

);

Port (in_C : IN STD_LOGIC_VECTOR (W_SIZE_CD-1 downto 0);

in_D : IN STD_LOGIC_VECTOR (W_SIZE_CD-1 downto 0);

CORR_ENA : IN STD_LOGIC;

ADRR_ROM : OUT INTEGER RANGE 0 to 255;

ADRR_RAM1 : OUT INTEGER RANGE 0 to 127;

ADRR_RAM2 : OUT INTEGER RANGE 0 to 127;

ADRR_RAM3 : OUT INTEGER RANGE 0 to 127;

ADRR_RAM4 : OUT INTEGER RANGE 0 to 127;

WE_RAM_1 : OUT STD_LOGIC;

INCD1 : IN STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0);

INCD2 : IN STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0);

INCD3 : IN STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0);

INCD4 : IN STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0);

CLK_160 : IN STD_LOGIC;

CD1 : OUT STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0);

CD2 : OUT STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0);

CD3 : OUT STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0);

CD4 : OUT STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0);

AD_RAM1 : IN INTEGER RANGE 0 to 63;

WE_RAM_2 : OUT STD_LOGIC;

RAM_IN : OUT STD_LOGIC_VECTOR(2*W_SIZE_CD-1 downto 0)

);

end mem_drv;

architecture Behavioral of mem_drv is

SIGNAL IWE_RAM_1: STD_LOGIC;

SIGNAL IWE_RAM_2: STD_LOGIC;

SIGNAL NCORR: STD_LOGIC;

SIGNAL RWR: STD_LOGIC;

SIGNAL DRWR: STD_LOGIC;

SIGNAL DDRWR: STD_LOGIC;

SIGNAL RW_EN: STD_LOGIC;

SIGNAL DNCORR: STD_LOGIC;

SIGNAL DDNCORR: STD_LOGIC;

SIGNAL CORR: STD_LOGIC;

SIGNAL COUNT: INTEGER RANGE 0 TO corr_depth;

SIGNAL DCOUNT: INTEGER RANGE 0 TO corr_depth;

SIGNAL DDCOUNT: INTEGER RANGE 0 TO (corr_depth/2)-1;

begin

NCORR <= not CORR_ENA;

RAM_IN(W_SIZE_CD-1 downto 0) <= in_C;

RAM_IN(2*W_SIZE_CD-1 downto W_SIZE_CD) <= in_D;

process (DDRWR)

begin

case DDRWR is

when '0'=> ADRR_RAM1 <= AD_RAM1;

ADRR_RAM2 <= AD_RAM1+64;

ADRR_RAM3 <= AD_RAM1;

ADRR_RAM4 <= AD_RAM1+64;

-------------------

CD1 <= INCD1;

CD2 <= INCD2;

CD3 <= INCD3;

CD4 <= INCD4;

when '1'=> ADRR_RAM1 <= DDCOUNT;

ADRR_RAM2 <= 0;

ADRR_RAM3 <= DDCOUNT;

ADRR_RAM4 <= 0;

-------------------

CD1 <= "000000000000";

CD2 <= "000000000000";

CD3 <= "000000000000";

CD4 <= "000000000000";

when others =>

ADRR_RAM1 <= 0;

ADRR_RAM2 <= 0;

ADRR_RAM3 <= 0;

ADRR_RAM4 <= 0;

-------------------

CD1 <= "000000000000";

CD2 <= "000000000000";

CD3 <= "000000000000";

CD4 <= "000000000000";

end case;

end process;

process (RWR)

begin

case RWR is

when '0'=> ADRR_ROM <=0;

when '1'=> ADRR_ROM <= COUNT;

when others => ADRR_ROM <= 0;

end case;

end process;

-- CD1 <= INCD1;

-- CD2 <= INCD2;

-- CD3 <= INCD3;

-- CD4 <= INCD4;

process (CLK_160) begin

IF RISING_EDGE (CLK_160)THEN

WE_RAM_1<=IWE_RAM_1;

WE_RAM_2<=IWE_RAM_2;

DRWR<=RWR;

DDRWR<=DRWR;

END IF;

RW_EN <=RWR or DRWR or DDRWR;

IF RISING_EDGE (CLK_160)THEN

IF DCOUNT < 127 and RWR = '1' THEN

IWE_RAM_1 <= '1';

IWE_RAM_2 <= '0';

ELSIF

DCOUNT >= 127 and RWR = '1'

THEN

IWE_RAM_1 <= '0';

IWE_RAM_2 <= '1';

ELSE

IWE_RAM_1 <= '0';

IWE_RAM_2 <= '0';

END IF;

DCOUNT <= COUNT;

DDCOUNT <= DCOUNT;

DNCORR <= NCORR;

DDNCORR <= DNCORR;

CORR <= (NOT DDNCORR) AND DNCORR;

END IF;

end process;

--

process (CLK_160) begin

IF RISING_EDGE (CLK_160)THEN

IF CORR = '1' THEN

RWR <= '1';

ELSIF

COUNT = 255

THEN

RWR <= '0';

ELSE RWR <= RWR;

END IF;

END IF;

end process;

process (CLK_160) -- counter

begin

IF RISING_EDGE (CLK_160)THEN

IF CORR = '1' THEN

COUNT <= 0;

ELSIF (RWR = '1') THEN

COUNT <= COUNT + 1;

ELSE

COUNT <= COUNT;

END IF;

END IF;

end process;

end Behavioral;

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