Реализация n-битного умножения на Spartan 3E Kit с использованием аппаратных умножителей

NET "P<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "P<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "P<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "P<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "P<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "P<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "P<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "A<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;

NET "A<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;

NET "A<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;

NET "A<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;

NET "load" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;

NET "rst" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN

ПРИЛОЖЕНИЕ Б

Листинг кода реализации 4-х разрядного умножения чисел без знака с использованием специализированного встроенного блока умножителя.

Sorce.vhd

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity sorce is

port (

A : in std_logic_vector (3 downto 0);

load, rst, clk: in std_logic;

P : out std_logic_vector (7 downto 0)

);

end sorce;

architecture Behavioral of sorce is

component mult4x4_u is

port (

A : in std_logic_vector (3 downto 0);

B : in std_logic_vector (3 downto 0);

P : out std_logic_vector (7 downto 0)

);

end component;

signal reg1: std_logic_vector (3 downto 0);

signal sA,sB :std_logic_vector (3 downto 0);

signal sP,sAA :std_logic_vector (7 downto 0);

signal s :std_logic;

begin

M1: mult4x4_u port map (A,reg1,sP);

process(clk, rst)

begin

if rst='1' then

reg1<="0000";

elsif clk='1' and clk'event then

if load='1'then

reg1<=A;

end if;

end if;

end process;

p2: process(clk)

begin

if clk='1' and clk'event then

p <= sP;

end if;

end process;

end Behavioral;

mult4x4_u.vhd

library IEEE;

use IEEE.std_logic_1164.all;

--

-- pragma translate_off

library UNISIM;

use UNISIM.VCOMPONENTS.ALL;

-- pragma translate_on

--

entity mult4x4_u is

port (

A: in std_logic_vector (3 downto 0);

B : in std_logic_vector (3 downto 0);

P : out std_logic_vector (7 downto 0)

);

end mult4x4_u;

--

architecture mult4x4_u_arch of mult4x4_u is

--

-- Components Declarations:

--

component MULT18X18

port (

A: in std_logic_vector (17 downto 0);

B: in std_logic_vector (17 downto 0);

P: out std_logic_vector (35 downto 0)

);

end component;

--

signal A_int : std_logic_vector (17 downto 0);

signal B_int : std_logic_vector (17 downto 0);

signal P_int : std_logic_vector (35 downto 0);

begin

A_int (17 downto 8) <= "0000000000";

A_int (7 downto 4) <= "0000";

A_int (3 downto 0) <= A (3 downto 0);

B_int (17 downto 4) <= "00000000000000";

B_int (3 downto 0) <= B (3 downto 0);

P (7 downto 0) <= P_int (7 downto 0);

--Multiplier Instantiation

U_MULT18X18: MULT18X18

port map (

A => A_int (17 downto 0),

B => B_int (17 downto 0),

P => P_int (35 downto 0)

);

end mult4x4_u_arch;

raspinovki.ucf

NET "clk" LOC = "C9"|IOSTANDARD = LVCMOS33;

NET "P<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "P<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "P<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "P<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "P<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "P<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "P<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "P<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "A<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;

NET "A<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;

NET "A<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;

NET "A<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;

NET "load" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;

NET "rst" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;

ПРИЛОЖЕНИЕ В

Структурно-функциональное представление устройства