Разработка автономного аппаратно-программного комплекса средств для подсистемы управления "Роботом-дозиметристом"

0,/*DW 0 ; displays "+" */

0,/*DW 0 ; displays "," */

g__,/*DW g ; displays "-" */

0,/*DW 0 ; displays "." */

0,/*DW 0 ; displays "/" */

/*30*/ a__+b__+c__+d__+e__+f__,/*DW a+b+c+d+e+f ; displays "0" */

b__+c__,/*DW b+c ; displays "1" */

a__+b__+g__+e__+d__,/*DW a+b+g+e+d ; displays "2" */

a__+b__+c__+d__+g__,/*DW a+b+c+d+g ; displays "3" */

b__+c__+f__+g__,/*DW b+c+f+g ; displays "4" */

a__+c__+d__+f__+g__,/*DW a+c+d+f+g ; displays "5" */

a__+c__+d__+e__+f__+g__,/*DW a+c+d+e+f+g ; displays "6" */

a__+b__+c__,/*DW a+b+c ; displays "7" */

a__+b__+c__+d__+e__+f__+g__,/*DW a+b+c+d+e+f+g ; displays "8" */

a__+b__+c__+d__+f__+g__,/*DW a+b+c+d+f+g ; displays "9" */

0,/*DW colon ; displays ":" */

0,/*DW 0 ; displays ";" */

0,/*DW 0 ; displays "<" */

0,/*DW 0 ; displays "=" */

0,/*DW 0 ; displays ">" */

0,/*DW 0 ; displays "?" */

0,/*DW 0 ; displays "@" */

/*41*/ a__+b__+c__+e__+f__+g__,/*DW a+b+c+e+f+g ; displays "A" */

0,/*DW 0 ; displays "B" */

a__+d__+e__+f__,/*DW a+d+e+f ; displays "C" */

0,/*DW 0 ; displays "D" */

a__+d__+e__+f__+g__,/*DW a+d+e+f+g ; displays "E" */

a__+e__+f__+g__,/*DW a+e+f+g ; displays "F" */

0,/*DW 0 ; displays "G" */

b__+c__+e__+f__+g__,/*DW b+c+e+f+g ; displays "H" */

b__+c__,/*DW b+c ; displays "I" */

b__+c__+d__+e__,/*DW 0 ; displays "J" */

0,/*DW 0 ; displays "K" */

d__+e__+f__,/*DW d+e+f ; displays "L" */

0,/*DW 0 ; displays "M" */

0,/*DW 0 ; displays "N" */

a__+b__+c__+d__+e__+f__,/*DW a+b+c+d+e+f ; displays "O" big*/

/*50*/ a__+b__+e__+f__+g__,/*DW a+b+e+f+g ; displays "P" */

0,/*DW 0 ; displays "Q" */

0,/*DW 0 ; displays "R" */

a__+c__+d__+f__+g__,/*DW a+c+d+f+g ; displays "S" */

0,/*DW 0 ; displays "T" */

c__+d__+e__+f__+b__,/*DW c+d+e+f+b ; displays "U" */

0,/*DW 0 ; displays "V" */

0,/*DW 0 ; displays "W" */

0,/*DW 0 ; displays "X" */

c__+d__+f__+g__+b__,/*DW e+f+g+b ; displays "Y" */

a__+b__+e__+g__+d__,/*DW a+b+e+g+d ; displays "Z" */

e__+f__+a__+d__,/*DW e+f+a+d ; displays "[" */

0,/*DW 0 ; displays "\" */

a__+d__+b__+c__,/*DW a+d+b+c ; displays "]" */

0,/*DW 0 ; displays "^" */

d__,/*DW d ; displays "_" */

/*60*/ 0,/*DW 0 ; displays " ' " */

0,/*DW 0 ; displays "a" */

c__+d__+e__+f__+g__,/*DW c+d+e+f+g ; displays "b" */

g__+d__+e__,/*DW g+d+e ; displays "c" */

b__+c__+d__+e__+g__,/*DW b+c+d+e+g ; displays "d" */

0,/*DW 0 ; displays "e" */

0,/*DW 0 ; displays "f" */

0,/*DW 0 ; displays "g" */

c__+e__+f__+g__,/*DW c+e+f+g ; displays "h" */

c__,/*DW c ; displays "i" */

b__+c__+d__+e__,/*DW b+c+d+e ; displays "j" */

0,/*DW 0 ; displays "k" */

b__+c__,/*DW b+c ; displays "l" */

0,/*DW 0 ; displays "m" */

e__+c__+g__,/*DW e+c+g ; displays "n" */

c__+d__+e__+g__,/*DW c+d+e+g ; displays "o" */

0,/*DW 0 ; displays "p" */

a__+b__+c__+f__+g__,/*DW a+b+c+f+g ; displays "q" */

e__+g__,/*DW e+g ; displays "r" */

0,/*DW 0 ; displays "s" */

d__+e__+f__+g__,/*DW 0 ; displays "t" */

c__+d__+e__ //,/*DW c+d+e ; displays "u" */

// 0,/*DW 0 ; displays "v" */

// 0,/*DW 0 ; displays "w" */

// 0,/*DW 0 ; displays "x" */

// 0,/*DW 0 ; displays "y" */

// 0,/*DW 0 ; displays "z" */

// 0,/*DW 0 ; displays "{" */

// e__+f__,/*DW e+f ; displays "|" */

// 0,/*DW 0 ; displays "}" */

// 0/*DW 0 */

};

void Config_LCD_Driver (void)

{

LCDBCTL0 = ~LCDON;

LCDBCTL0 = (LCDDIV2 + LCDDIV3) | (LCDPRE0 + LCDPRE1) | LCD4MUX;

LCDBPCTL0 = 0xFFFF;

LCDBPCTL1 = 0x00FF;

LCDBCTL0 |= LCDON;

}

void ClearDisplayDriverMemory(void)

{

int i;

char *LCD = LCDMEM;

for (i=0; i<12; i++)

{

LCD[i] = 0;

}

}

void Init_LCD (void)

{

Config_LCD_Driver();

ClearDisplayDriverMemory();

}

void Load_LCD_Memory(uchar* Video_Buffer)

{

ClearDisplayDriverMemory();

unsigned int temp;

char *mem;

mem = LCDMEM;

for (unsigned char i=0; i<8; i++)

{

temp = ascii_to_lcd_digit_e [Video_Buffer[i]-0x20];

*mem = (unsigned char)temp;

mem++;

temp = temp>>8;

*mem = (unsigned char)temp;

i++;

temp = ascii_to_lcd_digit_e [Video_Buffer[i]-0x20];

temp = temp<<4;

*mem |= (unsigned char)temp;

mem++;

temp = temp>>8;

*mem |= (unsigned char)temp;

mem++;

}

}

#include "msp430.h"

#include "RF_coreMod.h"

#define _HAL_PMM_DISABLE_SVML_

#define _HAL_PMM_DISABLE_SVSL_

#define _HAL_PMM_DISABLE_FULL_PERFORMANCE_

#ifdef _HAL_PMM_DISABLE_SVML_

#define _HAL_PMM_SVMLE SVMLE

#else

#define _HAL_PMM_SVMLE 0

#endif

#ifdef _HAL_PMM_DISABLE_SVSL_

#define _HAL_PMM_SVSLE SVSLE

#else

#define _HAL_PMM_SVSLE 0

#endif

#ifdef _HAL_PMM_DISABLE_FULL_PERFORMANCE_

#define _HAL_PMM_SVSFP SVSLFP

#else

#define _HAL_PMM_SVSFP 0

#endif

unsigned int SetVCore (unsigned char level)

{

unsigned int actlevel;

unsigned int status = 0;

level &= PMMCOREV_3; // Set Mask for Max. level

actlevel = (PMMCTL0 & PMMCOREV_3); // Get actual VCore

while (((level != actlevel) && (status == 0)) || (level < actlevel))

{

if (level > actlevel)

status = SetVCoreUp(++actlevel);

else

status = SetVCoreDown(--actlevel);

}

return status;

}

unsigned int SetVCoreUp (unsigned char level)

{

unsigned int PMMRIE_backup,SVSMHCTL_backup;

PMMCTL0_H = 0xA5;

cleared

PMMRIE_backup = PMMRIE;

PMMRIE &= ~(SVSMHDLYIE | SVSMLDLYIE | SVMLVLRIE | SVMHVLRIE | SVMHVLRPE);

possible

SVSMHCTL_backup = SVSMHCTL;

PMMIFG &= ~(SVMHIFG | SVSMHDLYIFG);

SVSMHCTL = SVMHE | SVMHFP | (SVSMHRRL0 * level);

while ((PMMIFG & SVSMHDLYIFG) == 0);

SVSMHCTL &= ~_HAL_PMM_SVSFP ;

if ((PMMIFG & SVMHIFG) == SVMHIFG){ //-> Vcc is to low for a Vcore increase

PMMIFG &= ~SVSMHDLYIFG;

SVSMHCTL = SVSMHCTL_backup;

while ((PMMIFG & SVSMHDLYIFG) == 0);

PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);

PMMRIE = PMMRIE_backup;

PMMCTL0_H = 0x00;

return PMM_STATUS_ERROR; // return: voltage not set

}

for a Vcore increase

SVSMHCTL |= SVSHE | (SVSHRVL0 * level);

SVSMLCTL = SVMLE | SVMLFP | (SVSMLRRL0 * level);

while ((PMMIFG & SVSMLDLYIFG) == 0);

PMMIFG &= ~(SVMLVLRIFG | SVMLIFG);

PMMCTL0_L = PMMCOREV0 * level;

if (PMMIFG & SVMLIFG)

while ((PMMIFG & SVMLVLRIFG) == 0);

PMMIFG &= ~SVSMLDLYIFG;

SVSMLCTL |= SVSLE | (SVSLRVL0 * level);

while ((PMMIFG & SVSMLDLYIFG) == 0);

SVSMLCTL &= ~(_HAL_PMM_DISABLE_SVSL_+_HAL_PMM_DISABLE_SVML_+_HAL_PMM_SVSFP );

PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);

PMMRIE = PMMRIE_backup;

PMMCTL0_H = 0x00;

return PMM_STATUS_OK; // return: OK

}

unsigned int SetVCoreDown (unsigned char level)

{

unsigned int PMMRIE_backup;

PMMCTL0_H = 0xA5;

cleared

PMMRIE_backup = PMMRIE;

PMMRIE &= ~(SVSMHDLYIE | SVSMLDLYIE | SVMLVLRIE | SVMHVLRIE | SVMHVLRPE);

PMMIFG &= ~(SVMHIFG | SVSMHDLYIFG | SVMLIFG | SVSMLDLYIFG);

SVSMHCTL = SVMHE | SVMHFP | (SVSMHRRL0 * level);

SVSMLCTL = SVMLE | SVMLFP | (SVSMLRRL0 * level);

while ((PMMIFG & SVSMHDLYIFG) == 0 || (PMMIFG & SVSMLDLYIFG) == 0);

PMMCTL0_L = PMMCOREV0 * level;

PMMIFG &= ~(SVSHIFG | SVSMHDLYIFG | SVSLIFG | SVSMLDLYIFG);

SVSMHCTL |= SVSHE | SVSHFP | (SVSHRVL0 * level);

SVSMLCTL |= SVSLE | SVSLFP | (SVSLRVL0 * level);

while ((PMMIFG & SVSMHDLYIFG) == 0 || (PMMIFG & SVSMLDLYIFG) == 0);

SVSMHCTL &= ~_HAL_PMM_SVSFP;

SVSMLCTL &= ~ (_HAL_PMM_DISABLE_SVSL_+_HAL_PMM_DISABLE_SVML_+_HAL_PMM_SVSFP );

PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);

PMMRIE = PMMRIE_backup;

PMMCTL0_H = 0x00;

if ((PMMIFG & SVMHIFG) == SVMHIFG)

return PMM_STATUS_ERROR; // Highside is still to low for the adjusted VCore Level

else return PMM_STATUS_OK; // Return: OK}

#include "RF_1_fun.h"

#include "cc430F6137.h"

unsigned char Strobe(unsigned char strobe)

{

unsigned char statusByte = 0;

unsigned int gdo_state;

if((strobe == 0xBD) || ((strobe >= RF_SRES) && (strobe <= RF_SNOP)))

{

RF1AIFCTL1 &= ~(RFSTATIFG);

while( !(RF1AIFCTL1 & RFINSTRIFG));

if ((strobe > RF_SRES) && (strobe < RF_SNOP))

{

gdo_state = ReadSingleReg(IOCFG2); // buffer IOCFG2 state

WriteSingleReg(IOCFG2, 0x29); // chip-ready to GDO2

RF1AINSTRB = strobe;

if ( (RF1AIN&0x04)== 0x04 ) // chip at sleep mode

{

if ( (strobe == RF_SXOFF) || (strobe == RF_SPWD) || (strobe == RF_SWOR) ) { }

else

{

while ((RF1AIN&0x04)== 0x04); // chip-ready ?

// Delay for ~810usec at 1.05MHz CPU clock, see erratum RF1A7

__delay_cycles(850);

}

}

WriteSingleReg(IOCFG2, gdo_state); // restore IOCFG2 setting

while( !(RF1AIFCTL1 & RFSTATIFG) );

}

else // chip active mode (SRES)

{

RF1AINSTRB = strobe;

}

statusByte = RF1ASTATB;

}

return statusByte;

}

unsigned char ReadSingleReg(unsigned char addr)

{

unsigned char data_out;

PATABLE

if ((addr <= 0x2E) || (addr == 0x3E))

RF1AINSTR1B = (addr | RF_SNGLREGRD);

else

RF1AINSTR1B = (addr | RF_STATREGRD);

while (!(RF1AIFCTL1 & RFDOUTIFG) );

data_out = RF1ADOUTB; // Read data and clears the RFDOUTIFG

return data_out;

}

void WriteSingleReg(unsigned char addr, unsigned char value)

{

while (!(RF1AIFCTL1 & RFINSTRIFG)); // Wait for the Radio to be ready for next instruction

RF1AINSTRB = (addr | RF_SNGLREGWR); // Send address + Instruction

RF1ADINB = value; // Write data in

__no_operation();

}

void ReadBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count)

{

unsigned int i;

if(count > 0)

{

while (!(RF1AIFCTL1 & RFINSTRIFG));

RF1AINSTR1B = (addr | RF_REGRD); for (i = 0; i < (count-1); i++)

{

while (!(RFDOUTIFG&RF1AIFCTL1));

buffer[i] = RF1ADOUT1B;

}

buffer[count-1] = RF1ADOUT0B;

}

}

void WriteBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count)

{

unsigned char i;

if(count > 0)

{

while (!(RF1AIFCTL1 & RFINSTRIFG));

RF1AINSTRW = ((addr | RF_REGWR)<<8 ) + buffer[0];

for (i = 1; i < count; i++)

{

RF1ADINB = buffer[i];

while (!(RFDINIFG & RF1AIFCTL1));

}

i = RF1ADOUTB;

}

}

void ResetRadioCore (void)

{

Strobe(RF_SRES);

Strobe(RF_SNOP);

}

void WriteRfSettings(RF_SETTINGS *pRfSettings) {

WriteSingleReg(FSCTRL1, pRfSettings->fsctrl1);

WriteSingleReg(FSCTRL0, pRfSettings->fsctrl0);

WriteSingleReg(FREQ2, pRfSettings->freq2);

WriteSingleReg(FREQ1, pRfSettings->freq1);

WriteSingleReg(FREQ0, pRfSettings->freq0);

WriteSingleReg(MDMCFG4, pRfSettings->mdmcfg4);

WriteSingleReg(MDMCFG3, pRfSettings->mdmcfg3);

WriteSingleReg(MDMCFG2, pRfSettings->mdmcfg2);

WriteSingleReg(MDMCFG1, pRfSettings->mdmcfg1);

WriteSingleReg(MDMCFG0, pRfSettings->mdmcfg0);

WriteSingleReg(CHANNR, pRfSettings->channr);

WriteSingleReg(DEVIATN, pRfSettings->deviatn);

WriteSingleReg(FREND1, pRfSettings->frend1);

WriteSingleReg(FREND0, pRfSettings->frend0);

WriteSingleReg(MCSM0 , pRfSettings->mcsm0);

WriteSingleReg(FOCCFG, pRfSettings->foccfg);

WriteSingleReg(BSCFG, pRfSettings->bscfg);

WriteSingleReg(AGCCTRL2, pRfSettings->agcctrl2);

WriteSingleReg(AGCCTRL1, pRfSettings->agcctrl1);

WriteSingleReg(AGCCTRL0, pRfSettings->agcctrl0);

WriteSingleReg(FSCAL3, pRfSettings->fscal3);

WriteSingleReg(FSCAL2, pRfSettings->fscal2);

WriteSingleReg(FSCAL1, pRfSettings->fscal1);

WriteSingleReg(FSCAL0, pRfSettings->fscal0);

WriteSingleReg(FSTEST, pRfSettings->fstest);

WriteSingleReg(TEST2, pRfSettings->test2);

WriteSingleReg(TEST1, pRfSettings->test1);

WriteSingleReg(TEST0, pRfSettings->test0);

WriteSingleReg(FIFOTHR, pRfSettings->fifothr);

WriteSingleReg(IOCFG2, pRfSettings->iocfg2);

WriteSingleReg(IOCFG0, pRfSettings->iocfg0);

WriteSingleReg(PKTCTRL1, pRfSettings->pktctrl1);

WriteSingleReg(PKTCTRL0, pRfSettings->pktctrl0);

WriteSingleReg(ADDR, pRfSettings->addr);

WriteSingleReg(PKTLEN, pRfSettings->pktlen);

}

void WriteSinglePATable(unsigned char value)

{

while( !(RF1AIFCTL1 & RFINSTRIFG));

RF1AINSTRW = 0x3E00 + value;

while( !(RF1AIFCTL1 & RFINSTRIFG));

RF1AINSTRB = RF_SNOP;

void WriteBurstPATable(unsigned char *buffer, unsigned char count)

{

volatile char i = 0;

while( !(RF1AIFCTL1 & RFINSTRIFG));

RF1AINSTRW = 0x7E00 + buffer[i];

for (i = 1; i < count; i++)

{

RF1ADINB = buffer[i];

while (!(RFDINIFG & RF1AIFCTL1));

}

i = RF1ADOUTB;

while( !(RF1AIFCTL1 & RFINSTRIFG));

RF1AINSTRB = RF_SNOP; }

void LFXT_Start(uint16_t xtdrive)

{

UCSCTL6_L |= XT1DRIVE1_L+XT1DRIVE0_L; startup

while (SFRIFG1 & OFIFG) {

UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG);

SFRIFG1 &= ~OFIFG; }

UCSCTL6 = (UCSCTL6 & ~(XT1DRIVE_3)) |(xtdrive); }

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